Ashish Mule
Summary
Seeking a rewarding career in VLSI physical design, where I can utilize my extensive knowledge of digital circuitry and proficiency in programming languages. With a deep-rooted enthusiasm for innovation and a keen eye for detail, I am determined to contribute to the growth of the organization Organized and dependable candidate successful at managing multiple priorities with a positive attitude. Willingness to take on added responsibilities to meet team goals.
Overview
1
1
Certification
Work History
Advanced VLSI Physical Design Course
Maven Silicon VLSI Training Center
Bangalore, India
August 2023 - Till Date
Education
Sinhgad College of Engineering
Pune, IndiaMahila Samiti English High School
Dombivali, IndiaVidya Niketan
Dombivali, IndiaSkills
HDL : Verilog
Programming Languages : Java
EDA Tools: ModelSim, Tanner, Tessent, Design Compiler, PrimeTime
Version Control : GIT
Operating Systems : Working knowledge of Windows and Linux
Domain : Physical design
Core Skills : RTL coding, simulation, FPGA, RISC-V, CMOS fundamentals, floor planning, placement and routing, static timing analysis, DFT, and sign-off (ERC, DRC, and LVS)
Additional Information
Router 1x3
• Router is an OSI layer 3 routing device that forwards data packets between computer networks.
• It drives an incoming packet to an output channel based on the address field contained in the packet header.
• The sub-modules of the router i.e. FIFOs, synchronizer, FSM block, and register are synthesized, simulated, and finally connected to its top module.
• Tools used: ModelSim and Design Compiler.
Smart Water Management System with Theft Detection
• This project aims to develop a water supply monitoring and regulation system using Arduino, a solenoid valve, and a flow sensor.
• The system will continuously monitor the water flow rate and send real-time data to a web server.
• In case of any water theft or leakage, an alert will be sent to the user.
• Tools used: Arduino and Proteus.
Certification
Digital Electronics:
Logic circuits, combinational and sequential circuits, finite state machines, and memories.
Verilog Programming:
Data types, operators, blocking and non-blocking assignments, delays in Verilog, begin-end and fork-join blocks, looping & branching constructs, system tasks and functions, compiler directives, FSM coding, synthesis issues, races in simulation, pipelining RTL & TB coding.
Static Timing Analysis:
STA basics, comparison with DTA, timing path and constraints, different types of clocks, clock domain and variations, clock distribution networks, fixing timing failure.
Design for Testability:
Basic testing principles, fault collapsing, DFT techniques, scan chain insertion, boundary scan, BIST.
Languages
• English
• Hindi
• Marathi
Affiliations
• Badminton
• Trekking
• Listening to music
Accomplishments
Secured 1st rank in inter-school and inter-college level badminton tournaments.
Timeline
Advanced VLSI Physical Design Course
Maven Silicon VLSI Training Center
Sinhgad College of Engineering
Mahila Samiti English High School
Vidya Niketan
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