Experienced ASIC Physical Design Engineer with 8 years in the semiconductor industry. Specializes in Netlist-to-GDSII flow, demonstrating proficiency in physical implementation of complex SoCs across technology nodes. Skilled in floorplanning, placement and routing, CTS, STA, IR/EM analysis, and physical verification using industry-standard EDA tools like Innovus, Tempus, and ICC2.
Overview
9
9
years of professional experience
Work History
Lead Design Engineer
Cadence Design System
07.2023 - Current
Worked on multiple DDR-IP designing projects (TSMC 7nm-6nm, Sec 5nm-4nm)
Responsibility: Bump planning, IO Placement, Signal and Power RDL routing, Power planning of DDR. Placement of sub macros and deciding the Size of DDR and Sub Macros.
Timing closure of high-speed DDR. Updating SPEC for driving CTS to meet the skew requirements and reduce timing violation.
DDR skew fixes and signoff checks (DRC Antenna LVS IR LEC).
Sr. Design Engineer
Intel Corporation
05.2022 - 07.2023
Responsible for 3 partition PNR.
Senior Design Engineer
Cadence Design System
03.2021 - 04.2022
Physical Design Engineer
Graphene Semiconductor Services Pvt. Ltd.
07.2017 - 03.2021
Project at NVIDIA: Two Low Power PCIE Chiplets on 10nm (sec10)
Responsibility: Working on netlist partitioning using ICC2DP. Handling netlist to GDS all PnR stage for Power, Timing, DRC signoff.
Project at NVIDIA: Two Padlet partition on 10nm (sec10)
Responsibility: ECO implementation and Power, DRC sign-off.
Challenges: Analyzing antenna, EM, power results and fixing DRC.
Project FARADAY (ODC): Two partitions on 28nm (UMC) with Low power design
Responsibility: Handling Netlist to GDS all PnR stages and Power, Timing, DRC, CLP sign-off for 2 blocks.
Challenges: High setup and hold violations because of skew groups balancing issue, analyzed problem and modified spec file to improve CTS QoR.
Few Logic groups ending CTS with high congestion not reflected in placement. Resolved congestion with use of multiple approaches simultaneously.
Project (ODC): Testchip on 55nm (UMC)
Responsibility: Handled netlist to GDS all PnR stages and closed design timing, power at optimum utilization.
Challenges: Concluding for optimum utilization considering post-route timing, DRC.
Handling custom routing for analog macros and script for power pad hookup with power ring.
Project (ODC): PPA analysis for Arm-A53. Technology: 22nm.
Responsibility: Setting up Synthesis, PnR flow and comparing post-route results on PPA matrix.
Challenges: Tuning Synopsis tools-based flow to drive block Synthesis, PnR and Timing closure.
Developing script to summarize data from all stages of PnR run and compare performance of Libraries.
SFQA ENGINEER
Marvell Semiconductors India Pvt. Ltd.
07.2016 - 07.2017
Education
M.Tech - VLSI & Embedded systems
College of engineering Pune
06.2016
Bachelor of Electronics and Telecommunication Engineering - undefined
Government College of Engineering Karad
Karad, MH
06.2014
Skills
Floor-planning
Power-planning
Place and route
CTS
STA
Timing closure
TCL scripting
DRC Fixing
LVS
Accomplishments
Gate percentile 99.45.
Stood first at college in MHT-CET.
Part of the state team which stood second at National level school games of tug of war.
Timeline
Lead Design Engineer
Cadence Design System
07.2023 - Current
Sr. Design Engineer
Intel Corporation
05.2022 - 07.2023
Senior Design Engineer
Cadence Design System
03.2021 - 04.2022
Physical Design Engineer
Graphene Semiconductor Services Pvt. Ltd.
07.2017 - 03.2021
SFQA ENGINEER
Marvell Semiconductors India Pvt. Ltd.
07.2016 - 07.2017
M.Tech - VLSI & Embedded systems
College of engineering Pune
Bachelor of Electronics and Telecommunication Engineering - undefined